1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and, more particularly, to a contactless, nonvolatile, metal oxide semiconductor (MOS) memory, and also to a method of fabricating the device.
2. Discussion of the Related Art
The fundamental structure of a conventional nonvolatile MOS memory cell is briefly described below with reference to FIG. 1, a sectional view of a simplified nonvolatile MOS memory cell with a stacked, floating gate configuration. More realistic configurations differ from the simplified configuration of FIG. 1 primarily in the shape and positioning of the gates.
As shown in FIG. 1, thin tunneling (gate) oxide 2 separates conductive floating gate 3 (the term floating gate refers to the fact that no electrical conductor is connected to this gate) and the channel of lightly-doped, p-type semiconductor substrate 1. Thick oxide 4 separates control gate 5 and the floating gate. Heavily-doped, n-type source/drain regions 6 lie within the substrate to either side of the floating gate.
The nonvolatile MOS memory cell illustrated in FIG. 1 may be viewed as simply a conventional MOS field effect transistor whose gate structure has been modified so as to enable semipermanent charge storage on the gate. The stacked, floating gate configuration is simply one technology by which charge retention on the gate has been realized. The charge stored on the gate gives rise to a threshold voltage shift, so that a nonvolatile, MOS memory with stored charge is at a higher-threshold-voltage state than the device with no stored charge. An impressed gate voltage, ultraviolet light, or some other technology may be used to eliminate the stored charge and return the device to its lower-threshold-voltage state. The charge-transfer mechanism of nonvolatile memory cells whose structures may be illustrated by FIG. 1 is based on tunneling through the thin gate oxide rather than on avalanche injection of hot electrons from the channel to the floating gate.
Nonvolatile MOC memory cells which have a stacked, floating gate configuration are favored for high-density applications due to their characteristically small cell sizes. Absent other changes, any reduction in cell size is necessarily accompanied by a decrease in the capacitive coupling between the control gate and the floating gate. To mitigate this effect of the reduction in cell size, a silicon dioxide/silicon nitride/silicon dioxide (ONO) composite dielectric, which has a higher breakdown voltage than a single oxide film, may be used as the insulator between the floating and control gates. The enhanced inter-gate capacitance due to use of an ONO dielectric comes at the price of the several processing steps, including a high temperature annealing, required to form the ONO sandwich, which result in a higher manufacturing cost and lower device yield per wafer.
Research is also continuing into the use of materials such as tantalum pentoxide, which has a significantly higher dielectric constant than silicon dioxide, as the insulator between the floating and control gates. At present, however, novel memory cell structures, rather than novel materials, appear to offer the most likely way to increase capacitive coupling while reducing effective memory cell size.
Since a conventional stacked, floating gate MOS memory device requires one metal contact for every two cells of the memory cell array, the size of an array of N stacked, floating gate memory cells is significantly greater than N times the size of a single memory cell. So-called contactless, nonvolatile memory cell technologies have been developed to counter this increase in effective cell size. A conventional contactless memory cell is described immediately below with reference to FIG. 2, a plan view of a contactless, nonvolatile MOS memory cell array, and FIG. 3, a sectional view of the device of FIG. 2 along line I-I'.
As shown in FIGS. 2-3, regularly-spaced, parallel pairs of heavily-doped, n-type source/drain regions 12 lie within a lightly-doped, p-type semiconductor substrate 11. A thin, tunneling dielectric film 17, typically a thermal oxide, covers the upper surface of the substrate. Insulating structures 15 isolate the source region of each of the above pairs of heavily-dope regions from the drain region of an adjacent pair of heavily-doped regions, and vice versa.
Regularly spaced, parallel, conductive control gates 13 above the substrate are perpendicular to the heavily-doped source/drain regions 12. Below any given control gate lie a plurality of conductive floating gates 14 on the dielectric film 17, each of which spans the interval between the members of one of the above pairs of source/drain regions. Insulating dielectric film 16 separates any given control gate from the floating gates below that control gate.
The memory device illustrated by FIGS. 2-3 includes a rectangular array of memory cells, each of which includes a single floating-gate, MOS transistor. The cells are interconnected by the control gates 37 extending along the row direction of the array and by the heavily-doped source/drain regions 12 extending along the column direction of the array. Each control gate serves as a word-line of the memory array, since it controls the movement of a bit into or out of the group of memory cells to which it is connected; the heavily-doped drain regions 12 serve as bit-lines of the array, since each transmits that bit to the rest of the system. The heavily-doped drain regions can serve as bit-lines due to their low bulk resistivity, so that metal lines need not be fabricated to serve this function. More importantly, the use of the heavily-doped drain regions as bit-lines means that a separate metal contact need not be formed to connect each memory cell to a bit-line, which results in a L,duced effective memory cell size.
Although the contactless, nonvolatile memory cell array illustrated by FIGS. 2-3 is characterized by a relatively large capacitive coupling between the control gate and the floating gate, the isolating structures 15 which serve to isolate any memory cell in the array froil the memory cells adjacent to it significantly increase the effective size of a memory cell.
U.S. Pat. No. 5,047,362, which issued on Sep. 10, 1991 to Albert Bergemont for Method for Making Large-Scale EPROM Memory with a Checker Board Pattern and an Improved Coupling Factor, which is hereby incorporated by reference in its entirety, discloses a contactless, nonvolatile memory which is characterized by relatively large intergate capacitive coupling but which does not employ insulating structures to isolate the memory cells of the array from each other. Such a memory array is described below with reference to FIG. 4, a plan view of the device, and FIG. 5, a sectional view of the device of FIG. 4 along line II-II'.
The nonvolatile memory device illustrated in FIGS. 4-5 comprises a matrix of memory cells interconnected by word-lines extending along the row direction of the matrix and bit-lines extending along the column direction of the matrix. Each memory cell comprises a symmetrical pair of floating-gate, MOS field effect transistors of the same row that share a common drain. Each of the two sources of a given memory cell is in turn shared with a transistor of an adjacent memory cell of the same row.
The memory cells are interconnected by the control gates 13 (word-lines) extending in the row direction of the matrix and by the heavily-loped drain regions 12b (bit-lines) extending along the column direction of the matrix. Heavily doped regions 12a and 12c adjacent to the heavily-doped region 12b between them serve as source regions. Regularly-spaced, parallel triplets of heavily-doped, n-type source/drain regions 12a, 12b, and 12c lie within lightly-doped, p-type semiconductor substrate 11. Thin tunneling oxide 17 covers the upper surface of the substrate.
Regularly-spaced, conductive first floating gates 14a, perpendicular to the heavily-doped regions 12, lie on the thin tunneling oxide and span the interval between the members of each pair of adjacent, heavily doped regions 12a and 12b. Regularly spaced, conductive first floating gates 14b, perpendicular to the heavily-doped regions 12, lie on the tunneling oxide and span the interval between the members of each pair of adjacent, heavily-dope regions 12b and 12c. Each first floating gate 14b which lies above a given heavily-doped region 12b is aligned with a first floating gate 14a which also lies above that heavily-doped region 12b, and vice versa. An insulating spacer 18 on tunneling oxide film 17 lies between each pair of aligned first floating gates 14a-14b.
A second floating gate 14c, perpendicular to the heavily-doped regions 12, lies on each pair of aligned first floating gates 14a-14b and on the insulating spacer 18 between the members of that pair of aligned first floating gates and is electrically connected to both members of the pair of first floating gates 14a-14b.
Regularly-spaced, parallel, conductive control gates 13, also perpendicular to the heavily-doped regions 12, lie on dielectric film 16, which covers the upper and lateral surfaces of second floating gates 14c. Below any given control gate 13 lie a plurality of second floating gates 14c. Each second floating gate 14c serves to increase the capacitive coupling between the first floating gates 14a and 14b below it and the control gate 13 above it.
Although the symmetric gate structure of the contactless, nonvolatile MOS memory device illustrated by FIGS. 4-5 does effectuate enhanced capacitive coupling between first floating gates 14a and 14b and the control gate 13 above them, any pair of first floating gates 14a and 14b share tunneling insulating film 17 with other pairs of first floating gates and are thereby coupled to them.